VHDL Programming

Day-1 (7 hours)

Entity
The data types used in input/output ports
Architecture
Data Objects
Constant Object
Signal Object
Variable Object
VHDL Operators
Assignment Operators
Logical Operators and Shift Operators
Relational Operators
Arithmetic Operators
Concatenation Operator "&"
Generic Statement
Combinational Logic Circuit Design and Concurrent Coding in VHDL
"When" and "Select" Statements
Generate Statement
Examples for combinational circuits implemented in VHDL
Simulation of VHDL Programs
Test-Bench Writing

Day-2 (7 hours)

User Defined Data Types, Arrays and Attributes
User Defined Data Types
Enumerated Types
User Defined Array Data Types
Constrained arrays
Unconstrained arrays
Defining PORT Arrays
Defining 2D Arrays or Matrices
Matrix as column wise concatenated row vectors
Matrix as Table of Numbers
3D Arrays
Subtypes
Type Conversion
Attributes of Data Types
Attributes for Scalar Data Types
Attributes for Array Data Types
Attributes for Signal Objects
Sequential Circuit Implementation in VHDL
Sequential Circuits in VHDL
Process
IF Statement
Example implementations for sequential logic units
D-type Flip Flop
Multiplexer
JK and T flip-flops
Counter
Clock Divider (Frequency Divider)
BCD to SS converter with 1 sec BCD counter
The wait statement
Wait until
Wait on
Case statement
Loop statements
Next and exit statements
Example sequential logic circuit implementation in VHDL
Implementation of Logic Circuits
Involving Registers and Counters
Shift Registers

Day-3 (7 hours)

Packages
Components
Functions and Procedures
Functions
Operator Overloading
Procedures
Differences Between a Function and a Procedure
Fixed and Floating Point Numbers
Fixed Point Numbers
Type Conversion Functions
Operators for fixed point numbers
Arithmetic Operations with Fixed Point Numbers and Sizing Rules
Automatic Resizing
Resize Function
Floating Point Numbers
Floating point type conversion functions
Operators for floating point numbers

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